Many circuits within integrated memory devices require a reference voltage for proper operation. For example, reference voltages are used in some memory devices which employ boosting amplifiers to compensate for losses in column select circuits that reduce line voltages from sense amplifiers. FIG. 1 shows boosting amplifiers 20 which are differential amplifiers that receive data D, D* from sense amplifiers on a pair of data lines 22 and output boosted data DX, DX* on a pair of output data lines 24. The boosting amplifiers 20 also include equilibration transistors 26 controlled by an equilibrate signal LEQ to reset the differential amplifiers and equilibrate the output data lines 24.
The responses of the boosting amplifiers 20 are controlled by respective current control transistors 30 that establish the maximum current I available to the boosting amplifiers 20, responsive to a reference voltage DCREF. When the sense amplifiers are inactive, the reference voltage DCREF is pulled low to disable the boosting amplifiers 20 and conserve power. To prepare for a data read operation, the reference voltage DCREF is pulled above the threshold voltage V.sub.T of the control transistors 30 to turn ON the control transistors 30. In response, the control transistors 30 establish the current I, thereby enabling the boosting amplifiers 20.
For example, if the data D, D* are high and low, respectively, they turn ON transistors 32, 34 and turn OFF transistors 31, 33. The ON transistors 32, 34 pull voltages V.sub.B, V.sub.D low at respective nodes B, D, inducing currents I.sub.36, I.sub.38 through respective diode-coupled PMOS transistors 36, 38. The induced currents I.sub.36, I.sub.38 establish gate voltages of the PMOS transistors 36, 38 and thus turn ON PMOS transistors 35, 37 to couple nodes A, C to the supply voltage Vcc. At the same time, the OFF transistors 31, 33 isolate respective nodes A, C from ground, so the voltages V.sub.A, V.sub.C at the nodes A, C rise to the supply voltage V.sub.CC. The nodes A, D drive the boosted data lines 24, such that the boosted data DX, DX* will be high and low, respectively.
For high speed operation, it is desirable to establish the reference voltage DCREF very quickly. FIG. 2 shows one prior art approach for providing the reference voltage DCREF, in which a reference voltage circuit 40 is formed from an inverter 42, a reset transistor 44, and a biasing leg 46. The reset transistor 44 is an NMOS transistor coupled between an output node 52 and ground with its gate controlled by the inverter 42. The biasing leg 46 is formed from a PMOS activation transistor 48, a PMOS dropping transistor 50 and a reference transistor 54 serially coupled between a supply voltage V.sub.CC and ground. The gate of the activation transistor 48 is controlled by the inverter 42 and the gates of the dropping and reference transistors 50, 54 are controlled by the output node 52.
The reference voltage circuit 40 is activated by an enable signal DCSA.sub.-- EN at the inverter input to initiate generation of the reference voltage DCREF. In response to the high enable signal DCSA.sub.-- EN, the inverter 42 outputs a low inverted enable signal DCSA.sub.-- EN* that turns OFF the reset transistor 44. Additionally, the low inverted enable signal DCSA.sub.-- EN* turns ON the activation transistor 48 to couple the supply voltage V.sub.CC to the dropping transistor 50. The dropping transistor 50 turns ON, because its source voltage (approximately V.sub.CC) is higher than its gate and drain voltage (approximately ground) because the reset transistor 44 was ON before DCSA.sub.-- EN* transitioned low. The ON dropping transistor 50 thus begins raising the voltage V.sub.NODE of the output node 52 toward the reference voltage DCREF. As the output node voltage V.sub.NODE rises, the gate-to-source voltage V.sub.GS of the reference transistor 54 rises above its threshold voltage V.sub.T and the reference transistor 54 turns ON. With all three transistors 48, 50, 54 ON the series combination of the transistors 48, 50, 54 will establish the reference voltage DCREF at a stable level determined by the channel resistances of the individual transistors 48, 50, 54.
When the enable signal DCSA.sub.-- EN returns low, the inverted enable signal DCSA.sub.-- EN* goes high, thereby turning OFF the activation transistor 48 and turning ON the reset transistor 44. The OFF activation transistor 48 isolates the output node 52 from the supply voltage V.sub.CC and the ON reset transistor 44 quickly pulls the output node 52 low preparing the reference voltage circuit 40 for the next high going transition of DCSA.sub.-- EN.
The above-described response of the reference voltage circuit 40 to DCSA.sub.-- EN going high will not be instantaneous, due to loading of the output node 52. As represented by a load circuit 56, circuits being driven by the reference voltage circuit 40 (e.g., the current control transistors 30 of FIG. 1 and the corresponding signal lines) load the reference voltage circuit 40. Such loading is primarily capacitive, so the load circuit 56 can be modeled adequately with a capacitor 58, as shown in FIG. 2.
The capacitance C of the load circuit 56 combined with the channel resistances of the transistors 48, 50, 54 forms an RC circuit such that the capacitor 58 charges exponentially to the reference voltage DCREF. Consequently, when the inverter 42 turns ON the upper PMOS transistor 48, the output node voltage V.sub.NODE rises toward the reference voltage DCREF at a rate determined by the RC time constant of the channel resistances and the capacitance C. The resulting delay in development of the reference voltage DCREF at the output node 52 slows operation of integrated device.
To improve the response time of the reference voltage circuit 40, another prior art reference voltage circuit 60 shown in FIG. 3 adds a timed boost circuit 62 to the reference voltage circuit 40 to provide a current boost to the output node 52 over a fixed period following transitions of the enable signal DCSA.sub.-- EN. The boost circuit 62 is formed from a pulse circuit 64 that drives a PMOS boost transistor 66 coupled between a supply voltage V.sub.CC and the output node 52. The pulse circuit 64 typically is formed from a NAND gate having one input driven by a re-inverted version of the inverted enable signal DCSA.sub.-- EN* and a second input driven by a delayed version of the inverted enable signal DCSA.sub.-- EN*. However, a variety of other circuit structures for the pulse circuit 64 will be apparent to one skilled in the art.
When the enable signal DCSA.sub.-- EN goes high and the inverted signal DCSA.sub.-- EN* goes low, the biasing leg 46 operates as described above. At the same time, the low-going inverted signal DCSA.sub.-- EN* activates the pulse circuit 64, thereby causing the pulse circuit 64 to output a low going pulse V.sub.P. The low-going pulse V.sub.P turns ON the boost transistor 66 for a fixed period .tau. to temporarily couple the supply voltage V.sub.CC to the output node 52. A boost current I.sub.BOOST flows through the ON boost transistor 66 to help charge the capacitor 58. Because the capacitor 58 is charged by both the boost current I.sub.BOOST and the current through the PMOS transistors 48, 50, the output node voltage V.sub.NODE rises more quickly to the reference voltage DCREF than in the circuit 40 of FIG. 2.
While the reference voltage circuit 60 of FIG. 3 provides an improved response time as compared to the reference voltage circuit 40 of FIG. 2, the circuit 60 does not always provide acceptable results, primarily because the duration of the current boost is fixed and unresponsive to the actual voltage of the output node 52. Consequently, it can be difficult to achieve proper timing of the boost signal to optimize the response. If the pulse V.sub.P is too long, the output node voltage V.sub.NODE may overshoot the desired reference voltage DCREF. Then, when the boost transistor 66 turns OFF, the biasing circuit 46 will require additional time to reduce the output node voltage V.sub.NODE to the reference voltage DCREF. If the pulse V.sub.P is too short, the boost current I.sub.BOOST will stop before the output node voltage V.sub.NODE reaches the reference voltage DCREF and the response of the circuit 60 will not be as fast as desired.
Establishing the proper pulse duration becomes even more problematic where the device includes more than one reference voltage circuit 60 or more than one boost amplifier 20. Such devices may be located at differing distances from the circuit 60. Consequently, the capacitance C presented to the reference voltage circuit 60 will vary according to the different lengths of signal lines between the reference voltage circuit 60 and the boost amplifiers 66. Consequently, the optimum duration .tau. of the pulse V.sub.P may depend upon the specific layout of the integrated device. Because the reference voltage circuit 60 of FIG. 3 uses a fixed time delay, the circuit 60 does not compensate for differences in capacitance C.